High-capacitance, on-chip capacitors are widely used in various types of digital and analog ICs such as dynamic random access memory (DRAM) and phase-lock loop (PLL), etc. Traditionally, such a capacitor is comprised of two sets of parallel metal wires embedded in different dielectric layers above a semiconductor substrate. The two sets of metal wires are alternately connected to the two opposite terminals of the capacitor. The capacitance of the capacitor is a function of the number of metal wires connected to one terminal, their respective length, width, and distance to neighboring metal wires connected to the other terminal. For example, a capacitor having longer metal wires usually has a higher capacitance providing that other geometric parameters remain the same.
Several shortcomings have been attributed to the aforementioned design of a capacitor structure. First, it is not flexible. Each specific design is associated with a fixed capacitance. If an IC requires a capacitance different from a previous design, a circuit designer has to compute a different set of geometric parameters for the corresponding capacitor structure. As a result, the IC manufacturing process has to be adjusted accordingly to fabricate the new capacitor structure. If an IC needs multiple on-chip capacitors, each having a unique capacitance, this may significantly increase the IC's design and manufacturing cost. Second, even though a longer metal wire may correspond to a higher capacitance, it is often accompanied by serious side effects. For example, a capacitor including longer metal wires tends to have higher parasitic resistance and inductance. This reduces the efficiency of the capacitor especially at higher frequencies.
In view of the aforementioned issues, there is a need for an on-chip capacitor structure that is easily adjustable to satisfy different capacitance requirements. It is also desirable that the capacitor structure have a better performance than conventional on-chip capacitors especially at high operating frequencies.